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DATASHEET
PCI-EXPRESS CLOCK SOURCE Description
The ICS557-03 is a spread spectrum clock generator that supports PCI-Express and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT's patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.
ICS557-03 Features
* Packaged in 16-pin TSSOP * Available in RoHS 5 (green) or RoHS 6 (green and lead * * * * * *
free) compliant packaging Supports HCSL or LVDS output levels Operating voltage of 3.3 V Input frequency of 25 MHz Jitter 80 ps (peak-to-peak) Spread Spectrum capability Industrial and commercial temperature ranges
Block Diagram
VDD 2
SS1:SS0 S1:S0
2
CLK0 Control Logic Phase Lock Loop CLK1 CLK1 CLK0
2
X1/ICLK 25 MHz crystal or clock X2 Optional tuning crystal capacitors
Clock Buffer/ Crystal Oscillator 2 GND OE
Rr(IREF)
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Pin Assignment
S0 S1 SS0 X1/ICLK X2 OE GNDXD SS1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDXD CLK0 CLK0 GNDODA VDDODA CLK1 CLK1 IREF
Output Select Table 1 (MHz) S1
0 0 1 1
S0
0 1 0 1
CLK(1:0), CLK(1:0)
25M 100M 125M 200M
Spread Selection Table 2 SS1
0 0 1 1
SS0
0 1 0 1
Spread%
No Spread Down -0.5 Down -0.75 No Spread
16-pin (173 mil) TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
S0 S1 SS0 X1/ICLK X2 OE GNDXD SS1 IREF CLK1 CLK1 VDDODA GNDODA CLK0 CLK0 VDDXD
Pin Type
Input Input Input Input Input Power Input
Pin Description
Select pin 0. See Table1. Internal pull-up resistor. Select pin 1. See Table 1. Internal pull-up resistor. Spread Select pin 0. See Table 2. Internal pull-up resistor. Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor. Connect to ground. Spread Select pin 1. See Table 2. Internal pull-up resistor.
Output Crystal connection. Leave unconnected for clock input.
Output Precision resistor attached to this pin is connected to the internal current reference. Output HCSL complimentary clock output 1. Output HCSL true clock output 1. Power Power Connect to voltage supply +3.3 V for output driver and analog circuits Connect to ground.
Output HCSL complimentary clock output 0. Output HCSL true clock output 0. Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
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Applications Information
External Components
A minimum number of external components are required for proper operation.
Output Structures
IREF =2.3 mA 6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01 F should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-03 to meet PCI Express specifications.
R R 475
See Output Termination Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. CL= Crystal's load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50 then RR = 475 , (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. Output Termination The PCI-Express differential clock outputs of the ICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.
General PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
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PCI-Express Layout Guidelines
Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
PCI-Express Device Routing
L1 RS L1' RS
L2 L2' RT L3' RT L3
L4 L4'
ICS557-03 Output Clock
PCI-Express Load or Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0 tOR
500 ps
500 ps
tOF 0.525 V 0.175 V
0.525 V 0.175 V
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LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm
LVDS Device Routing
L1 RQ L1'
L3 L3'
RP
RT ICS557-03 Clock Output
L2' L2
RT LVDS Device Load
Typical LVDS Waveform
1325 mV
1000 mV tOR 500 ps 500 ps tOF
1250 mV 1150 mV
1250 mV 1150 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDXD, VDDODA All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70 C -40 to +85 C -65 to +150 C 125 C 260 C 2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85 C
Parameter
Supply Voltage Input High Voltage1 Input Low Voltage1 Input Leakage Current
2
Symbo l
V VIH VIL IIL IDD IDDOE CIN COUT LPIN ROUT RPU
Conditions
Min.
2.97
Typ.
3.3
Max.
3.63 VDD +0.3 0.8 5 78 44 7 6 5
Units
V V V A mA mA pF pF nH k k
S0, S1, OE, ICLK, SS0, SS1 S0, S1, OE, ICLK, SS0, SS1 0 < Vin < VDD 50 2 pF , OE =Low Input pin capacitance Output pin capacitance CLK outputs S0, S1, OE, SS0, SS1
2.0 VSS-0.3 -5
Operating Supply Current Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor
3.0 100
1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V 10%, Ambient Temperature -40 to +85 C
Parameter
Input Frequency Output Frequency Output High Voltage1,2 Output Low Voltage1,2 Voltage1,2 Crossing Point Jitter,
Symbol
Conditions
HCSL termination LVDS termination
Min.
25 25 660 -150 250
Typ.
25
Max.
200 100
Units
MHz MHz MHz mV mV mV mV ps ppm
VOH VOL
HCSL HCSL Absolute Variation over all edges
700 0 350 80
850 27 550 140
Crossing Point Voltage1,2,4 Cycle-to-Cycle1,3 Frequency Synthesis Error Modulation Frequency Rise Time1,2 Fall Time1,2 Variation1,2 Rise/Fall Time Duty Cycle1,3 Output Enable Output Disable Time5 Time5 tSTABLE tSPREAD tOR tOF
All outputs Spread spectrum From 0.175 V to 0.525 V From 0.525 V to 0.175 V 30 175 175
0 31.5 332 344 33 700 700 125 50 45 55 10 10 3.0 3.0
kHz ps ps ps ps % us us ms ms
Output to Output Skew All outputs All outputs From power-up VDD=3.3 V Stabilization time after spread spectrum changes
Stabilization Time Spread Spectrum Transition Time
Note 1: Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Note 2: Measurement taken from a single-ended waveform. Note 3: Measurement taken from a differential waveform. Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
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Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case
Symbol
qJA qJA qJA qJC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Marking Diagram (ICS557G-03)
16 9
Marking Diagram (ICS557GI-03)
16 9
557G-03 ###### YYWW$$
1 8
557GI-03 ###### YYWW$$
1 8
Marking Diagram (ICS557G-03LF)
16 9
Marking Diagram (ICS557GI-03LF)
16 9
557G03LF ###### YYWW
1 8 1
557GI03L ###### YYWW
8
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" designates Pb (lead) free package. 4. "I" deisgnates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin of not USA.
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Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Inches* Min Max
Symbol
A A1 A2 b C D E E1 e L a aaa
Min
Max
E1 INDEX AREA
E
12 D
A2 A1
A
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
ICS557G-03 ICS557G-03T ICS557G-03LF ICS557G-03LFT ICS557GI-03 ICS557GI-03T ICS557GI-03LF ICS557GI-03LFT See Page 8
Marking
See Page 8
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
www.idt/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc. www.idt.com
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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